Nishkam Open Studio
Which Verilog / SystemVerilog works?

Your code is read by Yosys. Verilog-2005 works, and so do common SystemVerilog parts: always_ff, always_comb, logic and typedef enum. Interfaces, packages and classes do not work. Use plain modules and ports.

Write your design, then Submit.

Connect your machine

Work in progress: the local runner is not validated yet. Everything else on this site runs in your browser.

RTL problems run fully in your browser. Physical design (LibreLane on gf180) needs real tools, so it runs on your own computer through a small helper program. The website never gets your files; the helper only accepts this page and a secret token.

  1. Start the iic-osic-tools Docker container.
  2. Run the helper:
    python runner/nishkam_runner.py
  3. Open the link it prints. This page connects on its own.