Nishkam: free Verilog practice and chip design in browser

nishkam · Up-counter with enable

Easy

Up-counter with enable

Build a 4-bit up-counter. Synchronous active-high reset. Count when en=1, wrap from 15 to 0, hold otherwise.

Proved equal to a reference for every input sequence and every cycle after reset (by induction; if a proof is not possible, the result says it only covered the first 40 cycles).

See it

From code to layout.
This is the real thing.

01Write RTL
An editor with your design and its testbench, and one button to run the whole flow.
02See the schematic
Your Verilog drawn as logic, so you can check it is what you meant.
03Look at the layout
The finished GDS of tiny8, a small 8-bit CPU, on gf180mcuD, layer by layer.
04Check the timing
Real OpenSTA results: slack for every path.

Studio · Editor

Screenshots of Studio. The layout and timing come from a real run of tiny8.

The gap

Chip companies cannot hire
trained designers fast enough.

Learning IC design / chip design usually starts with a huge install. The open-source tool container we check Nishkam against is 25.2 GB. Many people never get past that first step.

1 to 23In the US there are 76,100 computer hardware engineers and 1,717,800 software developers (2025). US Bureau of Labor Statistics

67,000New US semiconductor jobs risk going unfilled by 2030. That is 58% of new jobs, and 61% of the gap is engineers and computer scientists. SIA and Oxford Economics, "Chipping Away", July 2023

85,000India has nearly 20% of the world's semiconductor design workforce and aims to train about 85,000 design engineers. Chips to Start-up has over 1 lakh enrolled and about 67,000 trained. MeitY Secretary, SEMICON India, 19 Sep 2026; PIB, 18 Jan 2026

Nishkam starts with a link. It is free, it runs in your browser with nothing to install, and it uses the real IC design flow, from RTL to layout.

How it works

Three simple steps.

01 · Write

Real problems

Write Verilog in a code editor. The problems are written by a working IC designer.

02 · Prove

Checked, not sampled

A solver tries to prove your design matches the reference for every input and every cycle after reset, so there are no hidden test cases. If it cannot finish the proof it checks the first 40 cycles and tells you. If something differs, you see the exact cycle.

03 · Harden

Take it to silicon

Turn a working design into a real layout: synthesis, placement, routing and checks, using open tools.

Grading

Every input.
Every cycle.

Your design and a reference are joined and handed to Yosys' SAT solver, running in your browser. It looks for any sequence of inputs that makes them disagree. When it finds one, you get that exact trace, not "test 7 failed".

cycle

clk

q expected

q yours

Cycle 13: expected 10, yours 0. Your counter wraps at 9.

Nishkam Studio · v0.1

The flow, step by step.

Everything here runs in your browser.

YosysVerilatorIcarus VerilogOpenSTAgraywolfTritonCTSqrouterMagicNetgenSurfer

Stage	Tools	Made by
Lint	Yosys, Verilator (verilator-wasm)	YosysHQ · Wilson Snyder
Simulation	Icarus Verilog	Stephen Williams
Waveforms	Surfer	Linköping University
Synthesis	Yosys + ABC, gf180mcu 7-track cells	YosysHQ · cells: Google + GlobalFoundries
Schematic	netlistsvg + ELK	Neil Turley
Placement	graywolf (qflow)	Yale University (TimberWolf)
Clock tree	OpenROAD TritonCTS (WebAssembly)	Mateus Fogaça, UFRGS
Routing	qrouter (qflow)	Tim Edwards
Timing	OpenSTA, before layout and after routing (with wires from Magic)	James Cherry, Parallax Software
DRC · GDS	Magic	UC Berkeley (Ousterhout and students); kept up by Tim Edwards
RC extraction	Magic (wires to SPEF, for timing)	as Magic above
LVS	Netgen	kept up by Tim Edwards, Open Circuit Design
Layout view	KLayout (kwasm) 2D / 3D · Tiny Tapeout Explorer 3D	Matthias Köfferlein · Alexander Mordvintsev

Nishkam gives back: we found and reported a bug in Netgen (netgen#111), fixed upstream in 1.5.325.

All open source. PDK: GlobalFoundries gf180mcuD.

In progress

What we are investigating next.

Research directions, not promises. We will add them as they prove useful.

Design for test: scan insertion and ATPG

Gate-level simulation

Formal verification (SymbiYosys)

SoC integration (FuseSoC)

IP packaging with Kactus2

PDK education: how a standard cell and its design rules are built

UVM-style verification

Analog design

FPGA flow

निष्काम (nishkām): doing the work fully, without craving the reward.

Learn chip designby doing it.

Up-counter with enable

Two things,
both free.

Problems to solve

A chip IDE in your browser

From code to layout.
This is the real thing.

A chip is a stack.
Scroll to pull it apart.

Chip companies cannot hire
trained designers fast enough.

Three simple steps.

Real problems

Checked, not sampled

Take it to silicon

Every input.
Every cycle.

Start anywhere.
From counters to chip area.

The flow, step by step.

What we are investigating next.

Up-counter with enable

Two things,both free.

Problems to solve

A chip IDE in your browser

From code to layout.This is the real thing.

A chip is a stack.Scroll to pull it apart.

Chip companies cannot hiretrained designers fast enough.

Three simple steps.

Real problems

Checked, not sampled

Take it to silicon

Every input.Every cycle.

Start anywhere.From counters to chip area.

The flow, step by step.

What we are investigating next.

Two things,
both free.

From code to layout.
This is the real thing.

A chip is a stack.
Scroll to pull it apart.

Chip companies cannot hire
trained designers fast enough.

Every input.
Every cycle.

Start anywhere.
From counters to chip area.